Utilizing Logical Implications for Verifying Accuracy of Exponentiation Functions in Embedded Systems Through XOR Operation

XVII International Conference on Systems, Automatic Control and Measurements, SAUM 2024 (pp. 121-124)

АУТОР(И) / AUTHOR(S): Jelena Nedeljković , Goran Nikolić , Tatjana Nikolić , Sandra Đošić 

Download Full Pdf  

DOI:  10.46793/SAUM24.121N

САЖЕТАК / ABSTRACT:

This paper introduces a novel method for verifying the accuracy of parameterized exponentiation functions within embedded systems. Leveraging logical implications, particularly through XOR operations, we examine the efficacy of error detection in these functions. By analyzing input and output bit patterns, our approach enhances precision and reliability in implementing exponentiation. Additionally, we explore implications for online error detection in logic circuits, aiming for efficient error detection with minimal hardware requirements. Our findings highlight the potential applications of logical implications in improving the accuracy and reliability of parameterized exponentiation within embedded systems.

КЉУЧНЕ РЕЧИ / KEYWORDS:

logical implications, embedded systems, error detection, parameterized exponentiation

ПРОЈЕКАТ / ACKNOWLEDGEMENT:

This work was supported by the Ministry of Science, Technological Development and Innovation of the Republic of Serbia [grant number 451-03-66/2024-03/200102].

ЛИТЕРАТУРА / REFERENCES:

  1. Nepal, N.Alves, J.Dworak, R. I.Bahar. Using Implications for Online Error Detection. In IEEE International Test Conference, Santa Clara, CA, USA, October 2008.
  2. Mitra and E.J. McCluskey. Which concurrent error detection scheme to choose? In Proceedings Interna tional Test Conference, pages 985–994, October 2000.
  3. Das and N. A. Touba. Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes. In VLSI Test Symposium, pages 309–315, 1998.
  4. N. Nedeljković, S.M. Đošić, G.S.Nikolić, A Survey of Hardware Fault Tolerance Techniques, ICEST, 2023.
  5. Glebov, S. Gavrilov, D. Blaauw, and V. Zolo tov. False-noise analysis using logic implications. ACM Trans. Des. Autom. Electron. Syst., 7(3):474 498, 2002.
  6. I.Bahar, M.Burns, G.Hachtel, E.Macii, H.Shin, and F.Somenzi. Symbolic computation of logic implications for technology-dependent low-power synthesis. In Proceedings of the International Symposium On Low Power Electronics And Design, pages163–168, Mon terey, CA, USA, August1996.
  7. Mohanram, E. Sogomonyan, M. Gossel, and N. Touba. Synthesis of low-cost parity-based partially self-checking circuits, 2003.
  8. K. Reinhardt and S. S. Mukherjee. Transient-fault detection via simultaneous multithreading. In Proceed ings of the 27th Annual International Symposium on Computer Architecture, pages 25–36, June 2000. (6-8)
  9. S. Sogomonjan and Michael Gossel. Design of self-parity combinational circuits for self- testing and on-line detection. In Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pages 239–246, Washington, DC, USA, 1993. IEEE Computer Society.
  10. Almukhaizim, P.Drineas, and Y.Makris. Cost driven selection of parity trees. In VLSI Test Symposium, pages 319–324,25-29 April2004.
  11. Umar Afzaal, Abdus Sami Hassan, Jeong-A Lee. Improved error detection performance of logic implication checking in FPGA circuits. In Microprocessors and Microsystems. July 2020.
  12. Alves, A. Buben, K. Nepal, J. Dworak, R.I. Bahar, A cost effective approach for online error detection using invariant relationships, IEEE Trans. Comput. Aided Des. Integr. Circuit Syst. 29 (5) (2010) 788-801
  13. H. Wang, T.Y. Hsieh, On probability of detection lossless concurrent error detection based on implications, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018) 1090-1103
  14. Abdus Sami Hassan, Revisiting Concurrent Error Detection Through Implication Selection Scheme, A thesis submitted in partial fulfillment of the requirements for a PhD degree